An Enhanced Low Power High Psrr Band Gap Voltage Reference Using Mosfets in Strong Inversion Region

In this paper, a band gap voltage reference using MOSFETs in strong inversion region is presented. The proposed circuit represents a high PSRR (Power Supply Rejection Ratio) and low temperature sensitivity and is capable of operating properly at supply voltages lower than 1v. In the designed circuit, the PSRR is improved using regulated voltage and a feedback loop. In addition, the circuit is independent on supply voltage noise. The circuit is designed in 180nm TSMC CMOS technology and is simulated using HSPICE. The obtained output voltage is 466.7mV and the obtained temperature deviation average under temperatures between -20°c to 100°c is 29.1 ppm/c°. PSRR is 109 dB at low frequencies. Calculated power dissipation with 1.2v supply voltage in room temperature is 42μw. KEYWORDS Band Gap Voltage Reference, Temperature Sensitivity, PSRR, Strong Inversion. 1. INTRODUCTION Band gap voltage reference is one of the most important blocks in many analog and digital systems, e.g., Analog to Digital and Digital to Analog Converters. In band gap voltage references, low temperature coefficient and high PSRR are strongly desired. Meanwhile, the voltage reference should provide low power dissipation and must be capable of operating properly at low supply voltages. Numerous types of voltage references and temperature sensors have been designed by means of Bipolar Junction Transistors (BJTs) due to their desired temperature features[1-2]. In fact, in most of the previous works, unequal current density of two BJTs is employed to generate a difference in Base Emitter voltage of the two transistors, making the Base-Emitter voltage of the two transistors (∆VBE) is directly proportional to temperature. On the other hand, it is known that the Base-Emitter voltage(VBE) is inversely proportional to temperature. HenceIn most band gap voltage reference circuits it is desired to sum up ∆VBE and Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 40 VBE in order to obtain a temperature-independent voltage reference. However, the aimed voltage reference might be practically challenging to obtain due to non-linear variations of VBE with temperature [3-5]. In this paper, a new technique is presented in order to address this problem. MOSFETs in strong inversion region are used in the place of BJTs. Furthermore, a regulated and improved current structure is used in order to obtain a high PSRR.Firstly, the proposed circuit is analysed. Afterwards, a feedback loop is inserted between the regulated voltage node and the operational amplifier. Utilizing the regulated voltage and the feedback loop leads toan improved PSRR. At last, the simulation results and conclusion are presented. [12] 2. THE PROPOSED BAND GAP VOLTAGE REFERENCE The Gate-Source voltage of NMOS transistors depends on electron mobility and threshold voltage, which is described in (1). = + (1) Where is the drain current of the transistor,  is the width-to-length ratio of the channel and Cox is unit capacitor of the Gate-Oxide. μ is the electron mobility and is the threshold voltage of N MOS transistor. The threshold voltage and electrons mobility dependence on temperature are given in (2) and (3) as mentioned in [6]. μ = μ ! !"#%& (2) V = V ( +∝)* T − T (3) where μ ,∝μ ,∝)* ,V ( are constant values and ∝μ ,∝)* are negative constants. and T are 300 kelvin and temperature coefficient, respectively. -μ in equation (2) ranges between -1 and 2. Therefore, the electron's mobility is inversely proportional to temperature. Since -. in equation (3) is negative, threshold voltage of NMOS is inversely proportional to temperature. The Gate-Source voltage of NMOS in equation(1) is capable of varying both inversely and directly with temperature. The first term produces the inverse relationship and the produces the direct relationship with temperature in VGS. Equation (4) shows variations of resistance with temperature. This phenomenon strongly affects both directly and inversely temperature-dependent currents in band gap voltage references and cause significant changes in the mentioned currents. The amount of resistance in the ambient temperature is shown as / bellow, which is dependent on fabrication process. However, temperature coefficients of 0and are constant values and are independent on fabrication process. R T = R T2 31 + TC0 T − T2 + TC T − T2 6 (4) Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 41 Thus, a resistor with smaller temperature coefficient is required. Consequently, unsolicited Poly silicon resistor in 180nm CMOS technology is utilized in the proposed circuit. Figure 1. General schematic of proposed band gap reference The structure of a band gap voltage reference using bipolar transistors with high PSRR is illustrated in fig.1. [7]. PSRR is improved in the circuit using regulated voltage of VREG. In this structure, regulated voltage and supply voltage have been separated. In contrast with the previously suggested band gap voltage references, the required decrease in supply voltage is equal to Source-Drain voltage in M6 and M7 transistors. In continue, the structure of the proposed band gap voltage reference using diode MOSFETs in strong inversion region is demonstrated in Fig. 2. +in and –in nodes in operational amplifier are equal. The voltage across R1 varies with temperature according to equations (5) and (6). Temperature behaviour of Gate Source voltage in diode transistors depend on the drain current and the size of the NMOS transistor. 70 = V8900 − V89 (5) V:0 = V* 00 + ;<= >?@ AB& # M00 − V* − ;<= >?@ AB& # M (6) Figure 2.Output voltage circuit for proposed band gap reference Channel length and drain current of M11 and M22 of equation (6) are equal and their threshold voltages are close. Hence, equation (6) can be simplified as equation (7) Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 42 V:0 = ;<= >?@ AB& # M00 − ;<= >?@ AB& # M (7) VR1 in equation (7) is subtraction of two temperature-dependent terms. In order to obtain variations in voltage across R1 which is proportional to temperature, first term must be greater than the latter. Consequently, using proper values for channel length in M11 and M22 diode transistors result in proportionally temperature-dependent voltage across R1. In other words, W22 must be greater than W11 and it must be W22=1.39W11. Current flowing through R1 resistor is calculated from equation (8). The current is obtained as a result of the difference in Gate-Source voltages of M11 and M22 across R1. Equation (9) suggests that the current flowing through M3 and M4 are proportional to IR1. I:0 = EFGHHIEFGJJ :H = ∆ELM :H (8) INO,Q = I:0 RSA ; TNU,V SA ; TNH,JW (9) Voltages of V1 and V2 nodes are the Gate-Source voltages of M33 and M44, respectively, which are diode connected in strong inversion region. The output voltages before connecting R4 and R5 is calculated from equation (10). vYZ[ = ELMUU 0\ :J :U ⁄ + ELMVV 0\ :U :J ⁄ (10) Equation (10) is more precisely expressed in equation (11). R2 and R3 are equal and do not have any effect on output temperature behaviour. vYZ[ = E^&UU\_R J`a= b?@ c%& WdUU 0\ :J :U ⁄ + E^&VV\_R J`a= b?@ c%& WdVV 0\ :U :J ⁄ (11) Where channel lengths of M3 and M4 are equal and their threshold voltages are close. Therefore, temperaturebehaviour of the Gate-Source voltage is only affected by the channel width of M33 and M44. In other words, M44 must be greater than M33 and should be WM33=2.38WM44. It is obvious from (9) that IR1 has proportionate changing with temperature and bias the M3 and M4 as a current mirror with equal currents. These equal currents bias the M33 and M44 with diode connecting in strong inversion. The (11) comprises two terms, the first one is V1 which has inverse relation with temperature ( V* OO > R ;<= >?@ Aμ& W MOO ), and the second term is V2 which is proportional to temperature Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 43 ( V* QQ < _R ;<= >?@ Aμ& WNVV). Fig.3. demonstrates how the value of voltage level is reduced using R4 and R5. In this circuit, the output voltage is calculated 466.7mv according to (12). ghij = klmn 0\RoJpqR H rsUUW∥ lusUU vW∥RoUpqR H rsVVW∥ lusVV vW oVpow (12) Fig. 3. Detailed schematic of proposed circuit The complete proposed band gap voltage reference including the main core, regulated supply voltage VREG, operational amplifier, start-up circuit and a module used to improve PSRR is shown in fig.4. The aspect ratio of the various parts utilized in the proposed circuit and the designed amplifier are given in table 1 and table 2, respectively. The utilized operational amplifier is a two stage op-amp with a high DC gain which is shown in fig.4. This characteristic causes improvement in PSRR and reduction in error rate in the output voltage. In order to reduce the input offset in the op-amp, M1-op and M2-op NMOS transistors with large aspect ratios have been used. Simulation results for the two-stage amplifier are given in table 3. Furthermore, nulling resistor technique is used for frequency compensation of this circuit in order to obtain appropriate phase margin and compensation network consisting of Cc and Rc. This operational amplifier is shown in fig.3. fig.4 shows the frequency response for the mentioned operational amplifier. Table1. Transistors aspect ratios of Fig.3 x. z{| }{| ⁄ | = ~ € zz ~{| ~}{| ⁄ | = ~ € ‚~ ƒ. ƒ{| }{| ⁄ | = ~ € „~ 952 f …~ ~}{| }{| ⁄ | = ~ € ‚† ƒ. ƒ{| }{| ⁄ | = ~ € „† ~z‡. ƒ‡ ˆ †. ~ˆ ⁄ rppo1rpo 22k ‰~ R € ŠW }{| }{| ⁄ | = ~ € „‹ †Œ{| }{| ⁄ | = † € „‡ Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 44 ~‡Œ.  ˆ †. ~ˆ ⁄ rppo1rpo 20k ‰† R € ŠW ƒ{| ~Œ{| ⁄ | = ~ € „‹~ †Œ{| }{| ⁄ | = † € „z ~‡Œ.  ˆ †. ~ˆ ⁄ rppo1rpo 20k ‰‡ R € ŠW ƒ{| ~Œ{| ⁄ | = ~ € „‹† ~Œ{| }{| ⁄ | = ~ € „} ~}ƒ ˆ †. ~ˆ ⁄ rppo1rpo 24k ‰z R € ŠW ~. zz{| }{| ⁄ | = ~ € „~~ ‡}{| }{| ⁄ | = } € „ zz. zx ˆ †. ~ˆ ⁄ rppo1rpo 71k ‰} R € ŠW †{| }{| ⁄ | = ~ € „†† }{| }{| ⁄ | = ~ € ƒ †Œ{| }{| ⁄ | = ~ € „‡‡ }{| }{| ⁄ | = ~ € „x Table2. Transistors aspect ratios of Op-Amp used in Fig.3 ~xˆ }ˆ ⁄  = † € „ƒIŽ ~}ˆ }ˆ ⁄  = ~ € „zIŽ ~Œ{| }{| ⁄ | = ~ € „~IŽ 1 Pf … ~†ˆ }ˆ ⁄  = ~ € „}IŽ ~Œ{| }{| ⁄ | = ~ € „†IŽ 50k ‘ ~~. ’ˆ }ˆ ⁄  = ~ € „IŽ ~}{| }{| ⁄ | = ~ € „‡IŽ Table3. Op-Amp simulation results Simulation Results Parameters 64 dB DC Gain 6.4 MHZ Unity Gain Bandwidth 59 degree Phase Margin ‡’. ƒ{“ Input Offset ~Œ. ‡x{” Current consumption Fig. 4. Frequency response of simulated Op-Amp 2.1 Start-up Circuit The startup circuit is shown in Fig.4.This circuit injects current into the core of Band Gap circuit. Ms1 transistor in startup circuit is combined with the high PSRR section in figure 4 In order to 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 -150 -100 -50 0 50 100 150 200 Frequency (Hz) Gain dB Phase degree Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 45 reduce power dissipation. Ms1 and Ms2 startup transistors are biased with supply voltage and drain of Ms1 is connected to the ground by capacitor (C1). Ms2 drain injects a current into the core of the Band Gap circuit. Mc copies a fraction of current of the core circuit from M1-M4 current mirror and uses it to bias the OP-AMP accompanied by Mc1 and M7-op.MC2 mirror transistor transfers Ib to M6 and M7 and the drain of MS1 startup transistor copies a partial current of M6 and M7 which causes increase in voltage across C1 to supply voltage value. Increase in voltage across the capacitor which is connected to MS2 gate makes MS1 and MS2 enter linear and cut-off regions, respectively. Finally proper current caused by by MS2 flows through the band gap voltage reference circuit. Gates voltages of MS1, MS2 and output voltage with versus startup circuit performance are shown in Fig.5. Settling time of the output voltage is 31μs. During settling time, startup circuit operation is independent from the core of the band gap circuit. Figure 5. Output voltage and gates voltages of Ms1 and Ms2 2.2 High Power Supply Rejection Ratio The PSRR in the proposed structure is enhanced using regulated voltage of Vreg. Mirror currents in M6 and M7 transistors provide regulated voltage Vreg as power supply for the core. The current source Ib which is shown in Fig.2 is independent from supply voltage and is a fraction of the current flowing through M1-M4. This structure separates the regulated voltage and supply voltage. This structure separates the regulated voltage from supply voltage. In comparison with the conventional band gap circuits, in this structure supply voltage required decrement is equal to the drain-source voltages of M6 and M7. In addition, M8 is biased in connection with M1-M4 in cascade configuration. The effects of supply voltage noise on regulated voltage Vreg is attenuated using following techniques. 1. Using Cascode current source configuration. 2. Utilizing a feedback loop. Feedback loop in Vreg node using a high gain op-amp amplifies the voltage difference between +in and –in nodes. 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 x 10 -5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Time(s) V o lt a g e (V ) Vgate(MS1) Vgate(MS2) Vref Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 46 The loop gain in this structure is relatively high and is calculated from (13). PSRR = klmn k × k ko˜L × ko˜L E™š = E›œ E™š #žŸZ žžŸ 0\;8 (13) Where Aop represents the operational amplifier gain, gm and ro are the transconductance and MOSFET output resistance, respectively. Since the size of M1 and M2 and the current flowing through them are equal, their transconductances are subsequently equal, gm1=gm2. 1/gm11 and 1/gm22 are small signal resistances of M11 and M12 as diode connected transistors. Large output resistances of M11 and M22 can be ignored in comparison with their small signal resistances.In addition, equivalent transconductance is gmeq which has been described in (14). R; = ¡¢ 0 £¤UU# ∥ ro§OO ̈ ∥ R + 23RQ + Ra6 « ∥ ¡¢ 0 £¤VV# ∥ ro§QQ ̈ ∥ RO + 23RQ + Ra6 « (14) PSRR for proposed circuit is presented in equation (15). g§­ = g§O + g§Q (15) Whew Vreg, Vref and Vac in (15) are supply voltage, output voltage and regulated voltage of proposed band gap reference, respectively. VYZ[ = V­ :V\:w :V\:w \: (16) 2.3 Simulation Results The proposed circuit is designed and simulated using TSMC 0.18μm technology with 1.2 V as supply voltage. Output voltage variations versus supply voltage are plotted in Fig.6 which is almost equal to the constant value of 466.7 mV for larger voltages. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 47 Figure 6. Output stage of Fig.2 circuit Output voltage variations versus temperature ranging from -20C° to 100C° is shown in Fig.7. Maximum deviation of output voltage in this range is 3.5 mV. Output voltage level is the lowest at 45C. Temperature coefficient of the output voltage for the simulated circuit is 29.16, which guarantees a reasonable temperature performance. Variations in V1 and V2 are shown in Fig.8. Fig 7. General part of high PSRR (Fig.3) Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 48 Figure 8. Small signal model of high PSRR part (Fig.7) Fig 9. Output voltage versus power supply variation Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 49 Fig 10. Output voltage versus temperature variation Fig 11. V1 and V2 versus temperature variation In order to investigate the effect of mismatch in transistors on performance of the circuit, monte carlo method must be deployed in simulations. Each transistor which is defined is associated with a Gaussian Sigma function obtained from technology. Obtained results from simulating 100 sample band gap reference are given in table 4. LG = AžŸ. £¤w £¤œ± 2 g§ ∗ R0 + 0 £sJJ ∥ ́μ¶ # # − g§0 ∗ 0 £sHH ∥ ́μ¶00 #· (17) g§Z ̧ = g§0 + g§ + g§­ + g§a (18) g§! = g§0 + g§ + g§a (19) Table 4. Simulation result of monte-carlo for proposed circuit 100 Sample Size 0.49014 Maximum Value in Sample 0.44015 Minimum Value in Sample 0.46715 Average in data in Sample -20 0 20 40 60 80 100 0.466 0.4665 0.467 0.4675 0.468 0.4685 0.469 0.4695 0.47 0.4705 Temperature(C) V R E F (V ) -20 0 20 40 60 80 100 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 Temperature(C) V 1 -V 2 V1 V2 Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 4, No 4, November 2015 50 0.46744 Median in data in Sample Fig 12. PSRR versus frequency for proposed circuit Table.5 PSRR in corner cases PSRR Process Corners 109 dB TT 102 dB TT+60 101 dB FS 106 dB SF 105 dB SS+120 111 dB FF-40 According to equation (16), considering 1σ and 3σ, maximum output voltage deviation (from its nominated value) are 15.62 ± mV and 22.97 mV, respectively. The simulated histogram for the proposed circuit is shown in fig.9. PSRR of the proposed band gap voltage reference with 1.2v supply voltage for 5 process corners with various temperatures in DC frequency are given in table 5. These results have been obtained corresponding to process corner of 60C TT+60, fast process corner of -40C FF-40, slow process corner with 120C SS+120 and other process corners. In continue, PSRR of the circuit in a range of frequencies is shown in figure 10. V­ V1o # open loop = E¿ EÀÁF × EÀÁF E™š (20) E¿ :` + E¿IEÀÁF Yž¤@ + g§ÂV£Ã = 0 (21) Table 6 shows the characteristics of the proposed band gap voltage reference in comparison with conventional works. "*" sign in table 6 denotes the results reported from fabrication process. All of the references in the table are simulated in CMOS technology. PSRR of the circuit is 109 dB at 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 -120 -100 -80 -60 -40 -20 0 Frequency(Hz) P S R R (d B )